1. Field
Embodiments relate to a semiconductor apparatus, and more particularly, to a method and circuit for tuning the phase of a data clock signal used to input and output data in a semiconductor apparatus.
2. Description of the Related Art
Dynamic random access memory (DRAM), for example, DDR1/2/3 and GDDR3/4, usually performs a core operation using a main clock signal and interfaces with a memory controller using a data strobe signal. In other words, data is transmitted in synchronization with the data strobe signal. The main operation of the core operation is accessing a memory cell array, i.e., a core of the DRAM, that is, writing data to or reading data from the memory cell array. At this time, the main clock signal and the data strobe signal have the same frequency. Therefore, when data is transmitted at a rising edge and a falling edge of the data strobe signal, the data is transmitted at a double data rate (DDR) with respect to the main clock signal. When a semiconductor apparatus operates in a DDR mode, a data interface speed is two times faster than a core speed.
With the development of high-speed graphics and games and the increase in speed of the memory controller, it is desired to increase the data interface speed of the semiconductor apparatus, e.g., DRAM. However, since it is very difficult to increase the speed due to the structure of the core circuit in the DRAM, there is a limit to increasing the frequency of the main clock signal. For this reason, only the data interface speed is increased by increasing the number of data bits or symbols input and output per command while the core speed of the DRAM is maintained in order to meet the requirements of systems. However, there is a limit to increasing the data interface speed with respect to the core speed of the DRAM while the main clock signal and the data strobe signal are maintained to have the same frequency in the DRAM.